| 高速SDRAM控制器设计的FPGA实现 |
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| 引用本文： | 张林,何春.高速SDRAM控制器设计的FPGA实现[J].电子科技大学学报(社会科学版),2008(Z1). |
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| 作者姓名： | 张林 何春 |
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| 作者单位： | 电子科技大学电子科学技术研究院;电子科技大学电子科学技术研究院 成都; |
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| 摘 要： | 同步动态存储器(SDRAM)控制器通常用有限状态机实现,对于一般的设计方法,由于状态数量多,状态转换通常伴随大的组合逻辑而影响运行速度,因此,SDRAM控制器的速度限制了SDRAM存储器的访问速度。该文从结构优化入手来优化方法,利用状态机分解的思想将大型SDRAM控制状态机用若干小的子状态机实现,达到简化逻辑的目的,不仅提高了速度还节省了资源,对该类大型SDRAM控制器的实现有一定参考意义。
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| 关 键 词： | 现场可编程门阵列 高速状态机 SDRAM控制器 状态机分解 |
FPGA Implementation of High Speed SDRAM Controller |
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| ZHANG Lin , HE Chun.FPGA Implementation of High Speed SDRAM Controller[J].Journal of University of Electronic Science and Technology of China(Social Sciences Edition),2008(Z1). |
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| Authors: | ZHANG Lin HE Chun |
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| Institution: | ZHANG Lin , HE Chun (Research Institute of Electronic Science , Technology,University of Electronic of Science , Technology of china Chengdu 610054) |
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| Abstract: | Synchronous dynamic random access memory (SDRAM) is widely used in nowadays digital systems for its large capacity and low price. The SDRAM controller is commonly implemented in finite state machine (FSM), which can not achieve high performance with complicated logic. As a result, the access speed is restricted. Taking advantages of the ideology of state machine decomposition, the SDRAM controller is implemented by several subordinate FSMs. This implementation can improve the speed and performance of the sy... |
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| Keywords: | field programmable gate array high-speed FSM SDRAM controller state machine decomposition |
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