A simulation study of dispatch rules for reducing flow times in semiconductor wafer fabrication

Semiconductor wafer fabrication involves very complex process routing, and reducing flow times is very important. This study reports a search for better dispatch rules for achieving the goal of reducing flow times, while maintaining high machine utilization. We explored a new simulation-based dispatch rule and a queue prediction dispatch rule. Using simulation experiments and an industrial data set, we also compared several other dispatch rules commonly used in semiconductor manufacturing with our proposed dispatch rules. Among these rules, in addition to the simulation-based dispatching rule, the shortest-remaining-processing-time, earliest-due-date and leastslack rules also performed well in terms of reducing flow times. The reasons behind these good rules are discussed in this paper. Based on the previous works and this study, accurately predicting and effectively utilizing future flow times can improve the quality of production management decisions.