| 双向并行移位链式浮点加速体系结构 |
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| 引用本文： | 陆文斌. 双向并行移位链式浮点加速体系结构[J]. 电子科技大学学报(社会科学版), 1992, 0(1) |
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| 作者姓名： | 陆文斌 |
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| 作者单位： | 电子科技大学微机所 |
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| 摘 要： | 研究计算机浮点运算的体系结构和浮点运算的逻辑加速问题.本文就浮点加速逻辑提出双向并行移位链式结构,并给出了该结构的逻辑实现方法.以此结构结合并行功能/数据浮点协处理器,可使计算机系统的浮点运算速度有数量级的提高.同时,还对该组成系统的 RISC模块结构进行了分析。
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| 关 键 词： | 浮点数 体系结构 并行移位链 浮点加速器 浮点协处理器 |
THE FLOATING-POINT ARITIIMETIC ACCELERATING SYSTEM STRUCTURE WITH TWO-WAY PARALLEL SHIFT CHAIN |
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| Lu Wenbin. THE FLOATING-POINT ARITIIMETIC ACCELERATING SYSTEM STRUCTURE WITH TWO-WAY PARALLEL SHIFT CHAIN[J]. Journal of University of Electronic Science and Technology of China(Social Sciences Edition), 1992, 0(1) |
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| Authors: | Lu Wenbin |
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| Abstract: | The system structure of floating-point arithmetic and the floating-point accelerating logic(FPA)are studied.It is put forward in the paper that a new structure is called floating-point accelerating logic with two-way parallel shift chain(TPSC).By the logic combined with the parallel function/data floating-point coprocessor,the rate of floating-point arithmetic in the computer system can be risen enormously.Sametime,the paper demon- strates the RISC construction of the floating-point arithmetic logic system. |
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| Keywords: | floating-point data system structure parallel shift chain floating-point accelerator floating-point coprocessor |
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