| 建立在De Bruijn图架构上的三维片上网络设计 |
| |
| 引用本文： | 陈亦欧,胡剑浩,凌翔.建立在De Bruijn图架构上的三维片上网络设计[J].电子科技大学学报(社会科学版),2011(2). |
| |
| 作者姓名： | 陈亦欧 胡剑浩 凌翔 |
| |
| 作者单位： | 电子科技大学通信抗干扰技术国家级重点实验室; |
| |
| 基金项目： | 国家863项目(2007AA01Z291); 教育部博士点基金新教师基金(200806141015) |
| |
| 摘 要： | 提出一种基于De Bruijn图的新型三维片上网络架构方式,利用De Bruijn图直径短、路由简单及容错等特性,实现三维片上网络水平面网络和虚平面网络相结合的分层架构与容错路由算法。利用仿真,在均匀流量和热点流量模型下将该架构与传统架构进行仿真与性能比较,结果表明,与传统的3D_Mesh、XNoTs等架构相比,基于De Bruijn图的三维片上网络架构方式具有较小的网络平均延时与良好的可扩展性。
|
| 关 键 词： | 三维集成电路 架构 网络延时 片上网络 功耗 |
3D Network on Chip Design Based on De Bruijn Graph Architecture |
| |
| CHEN Yi-ou,HU Jian-hao, LING Xiang.3D Network on Chip Design Based on De Bruijn Graph Architecture[J].Journal of University of Electronic Science and Technology of China(Social Sciences Edition),2011(2). |
| |
| Authors: | CHEN Yi-ou HU Jian-hao LING Xiang |
| |
| Institution: | CHEN Yi-ou,HU Jian-hao,and LING Xiang(The National Key Laboratory of Communication,University of Electronic Science and Technology of China Chengdu 610054) |
| |
| Abstract: | Since the three dimensional(3D) integrated circuit(IC) can offer shorter interconnection wire for network on chip(NoC),3D NoC becomes an emerging research area in recent years.This paper proposes a new architecture based on De Bruijn graph for 3D NoC.It makes use of advantages of De Bruijn graph,such as small diameter,simple routing,and high reliability to design a hybrid layering architecture combined by horizontal planer network and virtual horizontal planer network.It also adopts fault-tolerant routing a... |
| |
| Keywords: | 3D integrated circuits architecture network latency network on chip power |
| 本文献已被 CNKI 等数据库收录！ |
