| 芯片动态门限静态功耗的优化技术 |
| |
| 引用本文： | 李先锐,葛海波,来新泉,李玉山. 芯片动态门限静态功耗的优化技术[J]. 电子科技大学学报(社会科学版), 2009, 0(3) |
| |
| 作者姓名： | 李先锐 葛海波 来新泉 李玉山 |
| |
| 作者单位： | 西安电子科技大学电路设计研究所;西安邮电学院电信系; |
| |
| 基金项目： | 国家部委重点预研项目(D1120060967,Y30306270105); 教育部超高速电路与电磁兼容重点实验室专项项目(YZCB2008001) |
| |
| 摘 要： | 提出了一种双阈值电压的动态门限静态功耗优化算法。该算法通过直接统计电路门级节点的松弛裕度,利用静态时序分析其最大松弛裕度及邻节点松弛裕度特征,区分电路中的关键与非关键节点并分步调整其相应的阈值电压,从而有效地实现了对CMOS电路静态功耗的优化设计。基于ISCA85基准实验电路集,采用该技术和以往的算法进行了对比验证。结果表明,该算法在不降低静态功耗优化效率的同时,优化时间缩短了95%以上,适合于超大规模电路静态功耗优化。
|
| 关 键 词： | 双阈值 动态门限 静态功耗优化 静态时序分析 |
Optimization Techniques of Static Power Dissipation in Chip with Dynamical Threshold |
| |
| LI Xian-rui,GE Hai-bo,LAI Xin-quan , LI Yu-shan. Optimization Techniques of Static Power Dissipation in Chip with Dynamical Threshold[J]. Journal of University of Electronic Science and Technology of China(Social Sciences Edition), 2009, 0(3) |
| |
| Authors: | LI Xian-rui GE Hai-bo LAI Xin-quan LI Yu-shan |
| |
| Affiliation: | LI Xian-rui1,GE Hai-bo2,LAI Xin-quan1 , LI Yu-shan1 (1.Research Institute of Design Circuit,Xidian University Xi'an 710071,2.Department of Telecommunication,Xi'an Institute of Post , Telecommunications Xi'an 710061) |
| |
| Abstract: | A novel dynamic threshold static power optimization algorithm is presented.After accounting the relaxation margins of gate level nodes,the maximum margin in circuits and characteristics in adjacent gates are analyzed with static timing,the key and non-key nodes are then divided,their thresholds are adjusted within stages,and the efficient power optimization of CMOS circuits is finally implemented.Compared with existing algorithms,experimental results with ISCA85 benchmark circuits show that processing time ... |
| |
| Keywords: | Dual-threshold dynamical threshold static power optimization static timing analyzing |
| 本文献已被 CNKI 等数据库收录！ |
|
