Approximation scheme for restricted discrete gate sizing targeting delay minimization |
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Authors: | Chen Liao Shiyan Hu |
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Affiliation: | (2) Texas Instruments, Dallas, TX, USA |
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Abstract: | Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such that the delay of a combinational circuit is minimized while the cost constraint is satisfied. It is one of the most studied problems in VLSI computer-aided design. Despite this, all of the existing techniques are heuristics with no performance guarantee. This limits the understanding of the discrete gate sizing problem in theory. |
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