进位保留阵列乘法器的一种内建自测试

对进位保留阵列乘法器提出了一种内建自测试方案。设计实现了采用累加器生成测试序列和压缩响应,并提出了一种改进的测试向量生成方法。分析与实验结果表明,该方案能实现非冗余固定型故障的完全覆盖。由于乘法器在数据通路中常伴有累加器,该方案通过对已有累加器的复用,作为测试序列生成和响应压缩,减少了硬件占用和系统性能占用,同时具有测试向量少、故障覆盖率高的特点。

A Built-in Self-Test Scheme for Carry Save Array Multiplier

A built-in self-test scheme is presented for a carry save array multiplier in which an accumulator is designed as a test pattern generator and a response compactor. A modified deterministic test sequence is deduced. Analysis and Experiment results show that all the non-redundant stuck-at faults can be covered. As in current Very Large Scale Integration (VLSI) circuits accumulators commonly exist with multipliers, this scheme can lead to minimum hardware overhead and performance degradation by reusing available accumulators to generate test vectors and compact test responses. Moreover, this scheme can achieve the goal of short test sequences and high fault coverage.