| 高速整数开方电路的流水线设计 |
| |
| 引用本文： | 朱维乐,钱贵锁,杨刚,陈伟. 高速整数开方电路的流水线设计[J]. 电子科技大学学报(社会科学版), 2008, 0(2) |
| |
| 作者姓名： | 朱维乐 钱贵锁 杨刚 陈伟 |
| |
| 作者单位： | 电子科技大学电子工程学院;上海贝尔阿尔卡特有限公司;电子科技大学电子工程学院 成都;上海浦东新区; |
| |
| 摘 要： | 对一个位宽为32位整数的开方硬件电路的结构进行设计,介绍了应用流水线技术设计了一个高速求平方根电路,考虑FPGA的内部结构,对采用流水线技术之后占用的硬件资源进行了分析。提出了利用流水线实现开方问题的新算法,在一个时钟周期内对32位整数进行处理,计算出相应的平方根和余数并送出,在算法上具有精度高、速度快、易实现等优点。与传统的算法相比,它完全避免了除法的迭代,从而开方速度提高了一倍左右。
|
| 关 键 词： | 进位保存加法器 现场可编程门阵列 流水线结构 平方根 |
A Pipeline Architecture for High Speed Square Root |
| |
| ZHU Wei-le,QIAN Gui-suo,YANG Gang,, Chen Wei. A Pipeline Architecture for High Speed Square Root[J]. Journal of University of Electronic Science and Technology of China(Social Sciences Edition), 2008, 0(2) |
| |
| Authors: | ZHU Wei-le QIAN Gui-suo YANG Gang Chen Wei |
| |
| Affiliation: | ZHU Wei-le1,QIAN Gui-suo1,YANG Gang2,, Chen Wei1 (1. School of Electronic Engineering,University of Electronic Science , Technology of China Chengdu 610054,2. Alcatel Shanghai Bell Co. Ltd. Pudong Shanghai 201206) |
| |
| Abstract: | The technique about how to use pipeline architecture to design high speed square root hardware is illustrated through the process of designing a square root circuit of 32 bits integer. By taking into account of the capacity of FPGA,the resources consumed by the square root hardware is analyzed. The new method to solve the extraction of a root is presented,which can deal with the 32 bits sampled data within a clock period. This method is of high precision,fast speed,easily realization. Compared with the conv... |
| |
| Keywords: | carry save adder FPGA pipeline architecture square root |
| 本文献已被 CNKI 等数据库收录！ |
|
